This invention relates to a technique for fabrication of a semiconductor integrated circuit device and the semiconductor integrated circuit device fabricated by using this technique. Particularly, the present invention pertains to a technique which is effective when applied to a semiconductor integrated circuit device having a metal interconnection, which has, as a main conductive film, copper or the like, and is formed by depositing a thin copper film in a groove and removing a portion of the thin copper film from a region outside the groove by the CMP (Chemical Mechanical Polishing) method.
In the conventional semiconductor integrated circuit device, an interconnection film was formed, for example, by forming a thin film of a high-melting-point metal, such as aluminum (Al) alloy or tungsten (W), over an insulating film, forming a resist pattern having the same shape as that of the interconnection pattern over a thin film for interconnection by photolithography and then forming the interconnection pattern by dry etching using the resist pattern as a mask.
The conventional process using an Al alloy or the like is, however, accompanied with a drawback in that, attendant on miniaturization of the interconnection the interconnection resistance shows a marked increase, which inevitably increases an interconnection delay, resulting in a deterioration in the performance of the semiconductor integrated circuit device. Such a drawback has led to a serious problem particularly in a high-performance logic LSI and reprensents a factor for disturbing its performance.
The IBM J. Res. Develop., 39(4), the July issue, 419-435 (1995) or 1996 Symposium on VLSI Technology Digest of Technical Papers, pp 48-49, describes a process (so-called damascene method) for forming an interconnection pattern in a groove, which comprises embedding an interconnection metal, which has copper (Cu) as a main conductive film, formed in an insulating film and then removing an unnecessary portion of the metal outside the groove by the CMP (chemical machine polishing) method.
The Japanese Patent Application Laid-Open No. HEI 7-297183, describes a technique which comprises forming an interconnection groove on an insulating film formed over a semiconductor substrate, overlaying another insulating film, overlaying a conductive interconnection film, forming a planarizing film made of SOG (Spin On Glass) so as to embed the interconnection groove with the planarizing film, and polishing the planarizing film the and conductive interconnection film, thereby leaving an interconnection made of the conductive interconnection film in the interconnection groove.